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CY28339
Intel CK408 Mobile Clock Synthesizer
Features
* Compliant with Intel(R) CK 408 rev 1.1 Mobile Clock Synthesizer specifications * 3.3V power supply * Two differential CPU clocks * Nine copies of PCI clocks * Three copies configurable PCI free-running clocks * Two 48 MHz clocks (USB, DOT) * Five/six copies of 3V66 clocks Table 1. Frequency Table[1] S2 1 1 0 0 M S1 0 1 0 1 0 CPU (1:2) 100M 133M 100M 133M TCLK/2 3V66 66M 66M 66M 66M TCLK/4 66BUFF(0:2)/ 3V66(0:4) 66IN 66IN 66M 66M TCLK/4 66IN/3V66-5 66-MHz clock input 66-MHZ clock input 66M 66M TCLK/4 PCIF, PCI 66IN/2 66IN/2 33 M 33 M TCLK/8 REF 14.318M 14.318M 14.318M 14.318M TCLK USB/ DOT 48M 48M 48M 48M TCLK/2 One VCH clock One reference clock at 14.318 MHz SMBus support with read-back capabilities Ideal Lexmark profile Spread Spectrum electromagnetic interference (EMI) reduction * Dial-a-FrequencyTM features * Dial-a-dBTM features * 48-pin TSSOP package * * * *
Block Diagram
X1 X2
Pin Configuration
VDD_REF
PWR
XTAL OSC
REF XIN XOUT GND_REF VDD_CPU CPUT1:2 CPUC1:2 VDD_PCI PCIF
Stop Clock Control
Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 VDD_REF REF S1 CPU_STOP# VDD_CPU CPUT1 CPUC1 GND_CPU VDD_CPU CPUT2 CPUC2 IREF S2 USB_48MHz DOT_48MHz VDD_48 MHz GND_48 MHz 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA
PLL Ref Freq PLL 1
S1:2 VTT_PWRGD## CPU_STOP# Gate Divider Network
PWR Stop Clock Control
PCI7 PCI8 PCIF GND_PCI PCI0 PCI1 PCI2 VDD_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PD# VDD_CORE GND_CORE VTT_PWRGD#
PWR
PCI0:2 PCI4:8
CY28339
PCI_STOP# PD#
PWR
37 36 35 34 33 32 31 30 29 28 27 26 25
/2
VDD_3V66 3V66_0:1
PWR
3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN
PLL 2
VDD_48MHz
PWR
USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1
SDATA SCLK
SMBus Logic
Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the device's internal state register.
Cypress Semiconductor Corporation Document #: 38-07507 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised June 25, 2004
CY28339
Pin Definitions
Pin Number 47 1 2 43, 42, 39, 38 29 31 20 17, 18, 19 6 8, 9, 10, 12, 13, 14, 4, 5 35 34 36 46 37 21 30 45 24 REF0 XIN XOUT CPUT1,CPUC1 CPUT2, CPUC2 3V66_0 3V66_1/VCH 66IN/3V66_5 66BUFF [2:0] /3V66 [4:2] PCIF PCI [0:2] PCI [4:6] PCI [7:8] USB_48M DOT_48M S2 S1 IREF PD# PCI_STOP# CPU_STOP# VTT_PWRGD# Name I/O 3.3V 14.318-MHz clock output. 14.318-MHz crystal input. 14.318-MHz crystal input. Differential CPU clock outputs. 3.3V 66-MHz clock output. 3.3V selectable through SMBus to be 66 MHz or 48 MHz. 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO. 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO. 33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF default is free-running. PCI clock outputs divided down from 66Input or divided down from 3V66; PCI [7:8] are configurable as free-running PCI through SMBus.[2] Fixed 48-MHz clock output. Fixed 48-MHz clock output. Special 3.3V three-level input for Mode selection. 3.3V LVTTL inputs for CPU frequency selection. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for Power_Down# (active LOW). 3.3V LVTTL input for PCI_STOP# (active LOW). 3.3V LVTTL input for CPU_STOP# (active LOW). 3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1] inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. SMBus-compatible SDATA. SMBus-compatible SCLK. 3.3V power supply for outputs. Description
25 26 11, 15, 28, 40, 44, 48
SDATA SCLK VDD_PCI, VDD_3V66, VDD_CPU,VDD_RE F VDD_48 MHz VDD_CORE GND_REF, GND_PCI, GND_3V66, GND_IREF, GND_CPU GND_CORE
33 22 3, 7, 16, 27, 32, 41
3.3V power supply for 48 MHz. 3.3V power supply for phase-locked loop (PLL). Ground for outputs.
23
Ground for PLL.
Note: 2. PCI3 is internally disabled and is not accessible.
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Two-Wire SMBus Control Interface
The two-wire control interface implements a Read/Write slave only interface according to SMBus specification. The device will accept data written to the D2 address and data may read back from address D3. It will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent: 1. "Command code" byte 2. "Byte count" byte. Although the data (bits) in the command is considered "don't care," it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged.
Byte 0: CPU Clock Register[3,4] Bit 7 6 @Pu p 0 0 Name Description Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. CPU Clock Power-down Mode Select. 0 = Drive CPUT to 2x IREF and drive CPUC LOW 1 = Tri-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#. 3V66_1/VC H PCI_STOP# S2 S1 3V66_1/VCH Frequency Select 0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit. Reserved HW HW HW 1 Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP# is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin. Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only. Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only. Reserved
5 4 3 2 1 0
0
Byte 1: CPU Clock Register Bit 7 6 @Pu p 1 0 Name Reserved CPUT1, CPUC1 CPUT/C Output Functionality Control when CPU_STOP# is asserted. CPUT2, CPUC2 0 = Drive CPUT to 6x IREF and drive CPUC LOW 1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs will be three-stated. CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted. 0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit. CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted. 0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit. Reserved CPUT2, CPUC2 CPUT/C2 Output Control. 0 = disable, 1 = enabled. This is a Read and Write control bit. CPUT1, CPUC1 CPUT/C1 Output Control. 0 = disable, 1 = enabled. This is a Read and Write control bit. Reserved Description
5 4 3 2 1 0
0 0 0 1 1 1
Notes: 3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 - 1.8V and HIGH = > 2.0V. 4. The "Pin#" column lists the relevant pin number where applicable. The "@Pup" column gives the default state at power-up.
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Byte 2:PCI Clock Control Register (all bits are Read and Write functional) Bi t 7 6 5 4 3 2 1 0 @Pu p 0 1 1 1 1 1 1 1 PCI2 PCI1 PCI0 Nam e REF PCI6 PCI5 PCI4 Description REF Output Control. 0 = high strength, 1 = low strength. PCI6 Output Control. 0 = forced LOW, 1 = enabled PCI5 Output Control. 0 = forced LOW, 1 = enabled PCI4 Output Control. 0 = forced LOW, 1 = enabled Reserved PCI2 Output Control. 0 = forced LOW, 1 = enabled PCI1 Output Control. 0 = forced LOW, 1 = enabled PCI0 Output Control. 0 = forced LOW, 1 = enabled
Byte 3: PCIF Clock and 48M Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pu p 1 1 0 1 1 1 1 1 Name DOT_48 M USB_48 M PCIF PCI8 PCI7 PCIF PCI_8 PCI_7 Description DOT_48M Output Control. 0 = forced LOW, 1 = enabled USB_48M Output Control. 0 = forced LOW,1 = enabled PCI_STOP# Control of PCIF. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. PCI_STOP# Control of PCI8. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. PCI_STOP# Control of PCI7. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. PCIF Output Control. 0 = forced LOW, 1 = running PCI_8 Output Control. 0 = forced LOW, 1 = running PCI_7 Output Control. 0 = forced LOW, 1 = running
Byte 4: Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 1 1 1 3V66_0 3V66_1/VCH 3V66_5 19 18 66BUFF0/3V66_2 Name Reserved. Set = 0. 3V66_0 Output Enable. 0 = disable, 1 = enabled 3V66_1/VCH Output Enable. 0 = disable, 1 = enabled 3V66_5 Output Enable. 0 = disable, 1 = enabled 66BUFF2/3V66_4 Output Enable. 0 = disable, 1 = enabled 66BUFF1/3V66_3 Output Enable. 0 = disable, 1 = enabled 66BUFF0/3V66_2 Output Enable. 0 = disable, 1 = enabled Description SS2 Spread Spectrum Control Bit. 0 = down spread, 1 = center spread).
Byte 5:Clock Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 0 0 0 USB_48M DOT_48M Name Description SS1 Spread Spectrum Control Bit. SS0 Spread Spectrum Control Bit. 66IN to 66M delay Control MSB. 66IN to 66M delay Control LSB. Reserved. Set = 0. DOT_48M Edge Rate Control. When set to 1, the edge is slowed by 15%. Reserved. Set = 0. USB_48M edge rate control. When set to 1, the edge is slowed by 15%.
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Byte 6: Silicon Signature Register[5] (all bits are Read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 0 1 1 Vendor Code = 0011 Name Revision = 0001 Description
Byte 7: Reserved Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Description
Byte 8: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 N6, MSB N5 N4 N3 N2 N3 N0, LSB Name Reserved. Set = 0. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Byte 9: Dial-a-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from DAF (SMBus) registers. Name Reserved. Set = 0. These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Note: 5. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
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Dial-a-Frequency Features
SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. P is a large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 2. Table 2. P Value S(1:0) 00 01 10 11 P 32005333 48008000 96016000 64010667
Special Functions
PCIF and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. Any two of the PCIF clock outputs can be used as IOAPIC 33-Mhz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event that these clocks are not required, they can be used as general PCI clocks or disabled via the assertion of the PCI_STOP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. Configured as DRCG (66M), SMBus Byte0, Bit 5 = "0" The default condition for this pin is to power-up in a 66M operation. In 66M operation this output is SSCG-capable and when spreading is turned on, this clock will be modulated. Configured as VCH (48M), SMBus Byte0, Bit 5 = "1" In this mode, output is configured as a 48-Mhz non-spread spectrum output that is phase-aligned with other 48M outputs (USB and DOT) to within 1-ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power-on. When the SMBus Bit 5 of Byte 0 is programmed from a "0" to a "1," the 3V66_1/VCH output may glitch while transitioning to 48M output mode. PD# (Power-down) Clarification The PD# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the LOW "stopped" state. PD# Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66BUFF, the 66BUFF clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 x Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down.
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 3 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Table 3. Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread% +0.00, -0.25 +0.00, -0.50 +0.00, -0.75 +0.00, -1.00 +0.13, -0.13 +0.25, -0.25 +0.37, -0.37 +0.50, -1.50
3V66-0 PCI PCI_F
Tpci
Figure 1. Unbuffered Mode - 3V66_0 to PCI and PCIF Phase Relationship
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PWRDWN# CPUT 133MHz CPUC 133MHz PCI 33MHz 3V66 USB 48MHz REF 14.318MHz
Figure 2. Power-down Assertion Timing Waveforms - Unbuffered Mode
6 6 B u ff P C IF PW RDW N# CPU 133M Hz CPU# 133M Hz 3V66 6 6 In USB 48M Hz R E F 1 4 .3 1 8 M H z
Figure 3. Power-down Assertion Timing Waveforms Figure - Buffered Mode
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PD# Deassertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 3.0 ms.
<1.8m S
30uS m in 400uS m ax
66Buff1 / GMCH 66Buff PCIF / APIC 33MHz PCI 33M Hz PW RDW N# CPU 133MHz CPU# 133M Hz 3V66 66In USB 48MHz REF 14.318MHz
Figure 4. Power-down Deassertion Timing Waveforms - Buffered Mode CPU_STOP# Clarification The CPU_STOP# signal is an active LOW input used to synchronously stop and start the CPU output clocks while the rest of the clock generator continues to function. CPU_STOP# Assertion When CPU_STOP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STOP# will be stopped after being sampled by two falling CPUT/C clock edges. The final state of the stopped CPU signals is CPUT = HIGH and CPU0C = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 "select") x (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state.
CPU_STP# CPUT CPUC CPUT CPUC
Figure 5. CPU_STOP# Assertion Waveform
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CPU_STOP# Deassertion The deassertion of the CPU_STOP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner (meaning that no short or stretched clock pulses will be produces when the clock resumes). The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles.
CPU_STP# CPUT CPUC CPUT CPUC
Figure 6. CPU_STOP# De-assertion Waveform
Three-state Control of CPU Clocks Clarification
During CPU_STOP# and PD# modes, CPU clock outputs may be set to driven or undriven (tri-state) by setting the corresponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
PCI_STOP# Assertion The PCI_STOP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STOP# going LOW is 10 ns (tsetup) (see Figure 2.) The PCIF clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running.
t setup
P C I_S TP # P C IF 33M P C I 33M
Figure 7. PCI_STOP# Assertion Waveform PCI_STOP# Deassertion The deassertion of the PCI_STOP# signal will cause all PCI(0:2, 4:8) and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STOP# transitions to a HIGH level. The PCI STOP function is controlled by two inputs. One is the device PCI_STOP# pin number 34 and the other is SMBus Byte 0,Bit 3. These two inputs to the function are logically AND'ed. If either the external pin or the internal SMBus register bit is set LOW, the stoppable PCI clocks will be stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will return a 0 value if either of these control bits are set LOW (which indicates that the devices stoppable PCI clocks are not running).
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t setup
PCI_STP# PCIF PCI
Figure 8. PCI_STOP# Deassertion Waveform
VID (0:3), SEL (0,1) VTT_PWRGD# PWRGD
VDD Clock Gen Clock State State 0 Off Off
0.2-0.3mS Delay State 1
Wait for Sample Sels VTT_PWRGD# State 2 State 3 On On
Figure 9. VTT_PWRGD# Timing Diagram
S1
Device is not affected, VTT_PWRGD# is ignored.
Clock Outputs Clock VCO
S2 VTT_PWRGD# = Low
Delay >0.25mS
VDDA = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD3.3= off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 10. Clock Generator Power-up/Run State Program Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at the pin of the device. The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is 7% as shown in the current accuracy table.
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Table 4. CPU Clock Current Select Function Board Target Trace/Term Z Reference R, Iref - Vdd (3*Rr) Output Current Voh @ Z
50 50
Rr = 330 1%, Iref = 3.33mA Rr = 475 1%, Iref = 2.32mA
Ioh = 6*Iref Ioh = 6*Iref
1.0V @ 50 0.7V @ 50
Table 5. Group Timing Relationship and Tolerances Description Offset Tolerance 1.0 ns 1.0 ns 1.0 ns Conditions
3V66 to PCI USB_48M to DOT_48M Skew 66BUFF(0:2) to PCI offset
2.5 ns 0.0 ns 2.5 ns
3V66 leads PCI (unbuffered mode) 0 degrees phase shift 66BUFF leads PCI (buffered mode)
USB_48M and DOT_48M Phase Relationship
The USB_48M and DOT_48M clocks are in phase. It is understood that the difference in edge rate will introduce some inherent offset. When 3V66_1/VCH clock is configured for VCH (48-MHz) operation it is also in phase with the USB and DOT outputs. See Figure 11.
66BUFF(0:2) to PCI Buffered Clock Skew
Figure 13 shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The measurements were taken at 1.5V.
66IN to 66BUFF(0:2) Buffered Prop Delay
The 66IN to 66BUFF(0:2) output delay is shown in Figure 12.The Tpd is the prop delay from the input pin (66IN) to the output pins (66BUFF[0:2]). The outputs' variation of Tpd is described in the AC parameters section of this data sheet. The measurement taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 1 shows the timing relationship between 3V66_0 and PCI(0:2,4:8) and PCIF when configured to run in the unbuffered mode.
USB_48M DOT_48M
Figure 11. USB_48M and DOT_48M Phase Relationship
66IN
Tpd
66B
Figure 12. 66IN to 66BUFF(0:2) Output Delay Figure
66B PCI PCIF
1.53.5ns
Figure 13. Buffer Mode - 33V66_0; 66BUFF(0:2) Phase Relationship
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Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
1. Output impedance of the current mode buffer circuit - Ro (see Figure 14). 2. Minimum and maximum required voltage operation range of the circuit - Vop (see Figure 14). 3. Series resistance in the buffer circuit - Ros (see Figure 14). 4. Current accuracy at given configuration into nominal test load for given configuration.
The current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. The following parameters are used to specify output buffer characteristics:
VDD3 (3.3V +/- 5%)
Ro Iout
Slope ~ 1/R0
Ros 0V Iout 1.2V
Vout = 1.2V max
Figure 14. Buffer Characteristics Table 6. Host Clock (HCSL) Buffer Characteristics Characteristic Min.
Vout
Max.
Ro Ros Vout
3000 (recommended) N/A
N/A 1.2V
Table 7. Maximum Lumped Capacitive Output Loads Clock Max Load Units
PCI Clocks 3V66 66BUFF USB_48M Clock DOT_48M REF Clock
30 30 30 20 10 50
pF pF pF pF pF pF
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Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VDD VDD_A VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL
Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in.
-0.5 -0.5 -0.5 -65 0 - 2000 45 15 V-0 1
4.6 4.6 VDD + 0.5 150 70 150 -
V V VDC C C C Volts C/W C/W
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD_A, VDD_REF, VDD_PCI, VDD_3V66 , VDD_48, VDD_CPU IDD3.3V IPD3.3V CIN COUT LIN CXTAL
3.3 Operating Voltage
3.3 5%
3.135
3.465
V
Dynamic Supply Current Power Down Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance
All frequencies at maximum values PD# Asserted
- - - - -
280
mA mA
5 6 7 42
pF pF nH pF
Measured from the XIN
30
AC Electrical Specifications
Parameter Description Crystal Condition Min. Max. Unit
TDC TPERIOD T R / TF TCCJ TDC TPERIOD TPERIOD TPERIOD TPERIOD TSKEW TCCJ
XIN Duty Cycle
The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification Measured between 0.3VDD and 0.7VDD As an average over 1s duration
CPU at 0.7V
47.5
52.5 71.0 10.0 500 55 15.3 10.2 7.65 5.1 100 150
% ns ns ps % ns ns ns ns ps ps
XIN period XIN Rise and Fall Times XIN Cycle to Cycle Jitter CPUT and CPUC Duty Cycle 66MHz CPUT and CPUC Period 100MHz CPUT and CPUC Period 133MHz CPUT and CPUC Period 200MHz CPUT and CPUC Period CPUT/C Cycle to Cycle Jitter
When Xin is driven from an external clock source 69.841 - - 45 14.85 9.85 7.35 4.85 - -
Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX
Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX
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AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
T R / TF TRFM
TR TF
CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Crossing Point Voltage at 0.7V Swing
Measured from Vol= 0.175 to Voh = 0.525V Determined as a fraction of 2*(TR-TF)/(TR+TF)
175 - - - 280
700 20 125 125 430
ps % ps ps mv
VOX
CPU at 1.0 Volts
TDC TPERIOD TPERIOD TPERIOD TPERIOD TSKEW TCCJ T R / TF VOX
CPUT and CPUC Duty Cycle 66MHz CPUT and CPUC Period 100MHz CPUT and CPUC Period 133MHz CPUT and CPUC Period 200MHz CPUT and CPUC Period CPUT/C Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Crossing Point Voltage at 0.7V Swing
Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from Vol= 0.175 to Voh = 0.525V
45 14.85 9.85 7.35 4.85 - - 175 510 -
55 15.3 10.2 7.65 5.1 100 150 467 760 325
% ns ns ns ns ps ps ps mv ps
Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX
SE_ Slew Absolute Single-ended Rise/Fall Waveform Symmetry
3V66
TDC TPERIOD THIGH TLOW T R / TF TSKEWUNBUFFERED TSKEWBUFFERED TCCJ TDC T R / TF TSKEW TCCJ TPD TDC TPERIOD THIGH TLOW T R / TF TSKEW
3V66 Duty Cycle 3V66 Period 3V66 High Time 3V66 Low Time 3V66 Rise and Fall Times Any 3V66 to Any 3V66 Clock Skew Any 3V66 to Any 3V66 Clock Skew 3V66 Cycle to Cycle Jitter 66BUFF Duty Cycle 66BUFF Rise and Fall Times Any 66BUFF to Any 66BUFF Skew 66BUFF Cycle to Cycle Jitter
Measurement at 1.5V Measured at crossing point VOX Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V
66BUFF
45 15.0 4.95 4.55 0.5 - - - 45 0.5 - 2.5 45 30 12.0 12.0 0.5 -
55 15.3 - - 2.0 500 250 250 55 2.0 175 100 4.5 55 - - 2.0 500
% ns ns ns ns ps ps ps % ns ps ps ns % ns nS nS nS pS
Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V
PCI /PCIF
66IN to 66BUFF(Propagation Delay) Measurement at 1.5V PCI /PCIF Duty Cycle PCI /PCIF Period PCI and PCIF high time PCI and PCIF low time PCI and PCIF rise and fall times Measurement at 1.5V Measured at crossing point VOX Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
Document #: 38-07507 Rev. *A
Page 14 of 18
CY28339
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
TCCJ
PCIF and PCI Cycle to Cycle Jitter DOT_48M Duty Cycle DOT_48M Period DOT_48M Rise and Fall Times DOT_48M Cycle to Cycle Jitter USB_48M Duty Cycle USB_48M Period USB_48M Rise and Fall Times DOT_48M Cycle to Cycle Jitter
Measurement at 1.5V
DOT_48M
-
250
ps
TDC TPERIOD T R / TF TCCJ TDC TPERIOD T R / TF TCCJ
Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V
USB_48M
45 20.83 0.5 - 45 20.82 1.0 -
55 20.83 1.0 350 55 20.83 2.0 350
% ns ns ps % ns ns ps
Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V
REF
TDC TPERIOD T R / TF TCCJ TPZL/TPZH TPZL/TPZH TSTABLE TSS TSH TSU
REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Output Enable Delay (All Outputs) Output Disable Delay (All Outputs) Clock Stabilization from Power-up Stopclock Set Up Time Stopclock Hold Time Oscillator Start-up time
Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V
ENABLE/DISABLE and SETUP
45 1.0 - 1.0 1.0 -
55 4.0 1000 10.0 10.0 3.0 - -
% ns V/ns ps ns ns ms ns ns
69.827 69.855
When XIN is driven from external clock source
CPU_STOP# and PIC_STOP# set up time with respect to PCIF clock to guarantee that the effected clock will stop or start at the next PCIF clock's rising edge. When crystal meets min. 40 device series resistance specification
10.0 0
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CPUT TPCB
33.2 2p F 475
M easurem ent P oint
CPUC
TPCB
63.4
33.2 2pF
M easurem ent P oint
63 .4
3 30
Figure 15. 1.0V Test Load Termination
Document #: 38-07507 Rev. *A
Page 15 of 18
CY28339
33
TPCB
49.9 2pF
CPUT
Measurement Point
33
CPUC
49.9
TPCB
2pF
Measurement Point
475
Figure 16. 0.7V Test Load Termination
Output under Test Probe Load Cap 3.3V signals
-
tDC 3.3V
-
2.4V
1.5V
0.4V 0V Tr Tf
Figure 17. For Single-ended Output Signals
Ordering Information
Part Number Package Type Product Flow
CY28339ZC CY28339ZCT Lead Free CY28339ZXC CY28339ZCXT
48-pin TSSOP 48-pin TSSOP - Tape and Reel 48-pin TSSOP 48-pin TSSOP - Tape and Reel
Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
Document #: 38-07507 Rev. *A
Page 16 of 18
CY28339
Package Drawing and Dimensions
48-lead (240-mil) TSSOP II Z4824
0.500[0.019]
24 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG.
25
48
12.395[0.488] 12.598[0.496]
1.100[0.043] MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.100[0.003] 0.200[0.008]
51-85059-*C
Intel is a registered trademark of Intel Corporation. Dial-a-Frequency and Dial-a-dB are trademarks of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07507 Rev. *A
Page 17 of 18
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28339
Document History Page
Document Title: CY28339 Intel CK408 Mobile Clock Synthesizer Document Number: 38-07507 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A
122362 237868
12/13/02 See ECN
RGL RGL
New Data Sheet Added Lead Free Devices
Document #: 38-07507 Rev. *A
Page 18 of 18

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